Embodiments of the inventive concept described herein relate to heterogeneous computing systems including different kinds of processors and, more particularly, to controlling a cache coherency in heterogeneous computing systems.
As semiconductor technology advances, computing systems including a plurality of processors are being actively researched. In particular, an application range of a heterogeneous computing system that includes not homogeneous processors, but heterogeneous processors is widening based on various factors including the ability to process complicated and various operations, the increase in demand of a user, etc. A heterogeneous computing system may include, in general, a central processing unit (CPU) and a graphic processing unit (GPU).
The assignment of tasks may be important to improve the computing capability of heterogeneous computing systems. Relatively complicated operations, such as graphic processing, is typically performed by the GPU. Processing of a program and/or kernel by the GPU may not be completed at a GPU stage, and a result of the processing of the program and/or kernel by the GPU may be shared with the CPU. In this process, because data are shared between the CPU and the GPU, cache coherency issues may occur.
When considering the cache coherency of a heterogeneous computing system, a workload of a program and/or kernel to be processed by the GPU is typically not considered. In general, the cache coherency is controlled in consideration of a cache hit or a cache miss. Therefore, when data sharing between the CPU and the GPU is frequent, a program and/or kernel may be processed in a non-cache coherent manner. When data are rarely or infrequently shared between the CPU and the GPU, a program and/or kernel may be processed in a cache coherent manner. The above-described data processing and cache management may not be desirable in terms of resource management, power management, and performance of a system.